CYRF6936
Document #: 38-16015 Rev. *F Page 2 of 39
Figure 5-1. CYRF6936, 40 QFN – Top Vie
5.0 Pin Descriptions
Pin # Name Type Default Description
13 RF
N
I/O I Differential RF signal to/from antenna
11 RF
P
I/O I Differential RF signal to/from antenna
10 RF
BIAS
O O RF I/O 1.8V reference voltage
30 PACTL I/O O Control signal for external PA, T/R switch, or GPIO
1 XTAL I I 12-MHz crystal
29 XOUT I/O O Buffered 0.75, 1.5, 3, 6 or 12 MHz clock, PACTL, or GPIO.
Tristates in sleep mode (recommend configure as GPIO drive low).
25 SCK I I SPI clock
28 MISO I/O Z SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).
Tristates when SPI 3PIN=0 and SS
deasserted.
27 MOSI I/O I
SPI data input pin (Master Out Slave In), or SDAT
24 SS I I SPI enable, active low assertion - enables and frames transfers.
26 IRQ I/O O Interrupt output (configurable active high or low), or GPIO
34 RST I I Device reset. Internal 10k-ohm pull-down resistor. Active HIGH,
typically connect via 0.1-µF capacitor to V
BAT
37 L/D O PMU inductor/diode connection
40 V
REG
Pwr PMU boosted output voltage feedback
35 V
DD
Pwr Decoupling pin for 1.8V logic regulator, connect via 0.47-µF capacitor
to GND
6, 8, 38 V
BAT
Pwr V
BAT
= 1.8V to 3.6V. Main supply.
3, 7, 16 V
CC
Pwr V
CC
= 2.4V to 3.6V. Typically connected to V
REG
33 V
IO
Pwr I/O interface voltage, 1.8–3.6V
19 RESV I Must be connected to GND
2, 4, 5, 9, 14, 15, 18, 17, 20,
21, 22, 23, 32, 36, 39, 31
NC NC Recommend to connect to GND
12 GND GND Ground
E-PAD GND GND Ground
CYRF6936
40-lead QFN
RF
BIAS
NC
NC
V
BAT
V
CC
V
BAT
XTAL
V
CC
NC
NC
V
REG
NC
NC
V
BAT
L/D
NC
NC
V
IO
V
DD
RST
RF
N
NC
NC
V
CC
NC
NC
RESV
NC
GND
RF
P
NC
SS
SCK
IRQ / GPIO
MOSI / SDAT
MISO / GPIO
XOUT / GPIO
PACTL / GPIO
NC
NC
23
24
25
26
27
28
29
30
22
21
13
14
15
16
17
18
19
20
12
11
10
9
2
8
7
6
1
3
5
4
40
39
32
38
37
36
31
33
35
34
* E-PAD BOTTOM SIDE
CYRF6936
Top View*
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